IC-MHM Datasheet, PDF (33/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
TEST MODE
Rev D1, Page 33/63
Test Mode (TEST)
Test mode is used to measure the internal bandgap and
reference voltages, and to set the bias current.
TEST
Value
0x00
0x01 ...
0x18
0x19
0x1A ...
0x1F
Address 0x07; bits 4:0
Description
Normal Operation
Reserved (Do not use)
Test Mode
Reserved (Do not use)
In Test Mode (TEST = 0x19), the internal bandgap volt-
age is output on PCOS (pin 18), the internal reference
voltage used for signal conditioning is output on PSIN
(pin 4), and the internal bias current can be measured
at NSIN (pin 3).
Refer to Elec. Char. item no. 401- 403 for more in-
formation on the voltage and current ranges. Refer
to CALIBRATION on page 54 for more information on
setting the bias current.
Table 55: Test Mode
EEPROM AND I²C INTERFACE (Multi-master)
The iC-MHM contains a dedicated I²C interface (pins
SCL and SDA) for use with an external serial EEP-
ROM. This EEPROM is typically used in stand-alone
applications for storage of configuration data (parame-
ter values). The interface is multi-master, allowing the
same EEPROM to be accessed by an external multiturn
sensor (such as iC-PV or iC-MV) for storage of its own
configuration data.
Mode on page 46 and CONFIGURATION on page 52
for more information. An external EEPROM connected
to the iC-MHM’s I²C interface cannot be accessed using
SPI.
Basic interface features
The external EEPROM is only accessible by the
iC-MHM via the BiSS interface. In stand-alone appli-
cations using SSI or incremental outputs, the iC-MHM
must be configured using BiSS and the parameter val-
ues stored in the EEPROM. Refer to SERIAL INTER-
FACE: BiSS Mode on page 37 and CONFIGURATION
on page 52 for more information.
I2C Master Performance
Protocol
Standard I²C
Clock Rate (Output)
100 kHz max. (refer to Elec. Char. 714)
Addressing
11 bit: 8 bit register address plus
3 bit block selection
Multi-Master Capability Yes
Table 56: I²C interface performance
In embedded applications, the iC-MHM is typically con-
figured using the SPI interface and parameter value
storage is handled by the SPI master (host processor
or microcontroller). Refer to SERIAL INTERFACE: SPI
The I²C master of iC-MHM addresses I²C devices us-
ing an 8-bit register address plus 3 block selection bits
as part of the I²C slave address.
SCL
fclk(SCL)
SDA
S 1 0 1 0 A10 A9 A8 W ACK A7 ... A0 ACK D7 … D0 ACK P
Start
cond.
Slave Address
Write ACK Slave Address
(4 bit Device ID + upper 3 bits of 11 Bit address)
lower 8 bits
ACK
Data (8 bit)
ACK
Stop
cond.
Figure 18: I²C slave addressing for writing a single byte to the EEPROM.
If addressing a memory of 1 Kbit or 2 Kbit, the block se- is 0x50 (for ’1010 000’ without the R/W bit), or 0xA0
lections bits are zero and thus the I²C device address respectively (for ’1010 0000’ with the R/W bit as zero).