IC-MHM Datasheet, PDF (34/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
Rev D1, Page 34/63
EEPROM device requirements
EEPROM Device Requirements
Supply Voltage
3.3 V to 5.5 V
(respectively according to VDD)
Power-On Threshold
< 3.3 V (due to Elec.Char. 404)
Addressing
11 bit address max.
Device Address
0x50 (’1010 000’ w/o R/W bit),
0xA0 (’1010 0000’ with R/W = 0)
Page Buffer
Not required
Size Min.
1 Kbit (128x8 bit), type 24C01,
for configuration data
Size Max.
16 Kbit (8x 256x8 bit), type 24C16
Size limited due to 11-bit slave
addressing.
Table 57: EEPROM Device Requirements
In stand-alone applications, configuration data for both
the iC-MHM and external multiturn devices are stored
in the EEPROM and protected by checksums.
Address
Range
0x00 ...
0x0F
0x10 ...
0x1B
0x1C
0x1D ...
0x22
0x23
0x24 ...
0x3F
Description
Multiturn Configuration Data
iC-MHM Configuration Data
iC-MHM Configuration Checksum
iC-MHM Offset Data
iC-MHM Offset Checksum
Reserved (Must Be Zero)
Table 58: EEPROM Configuration Data Storage
Configuration data for an external multiturn device
(such as iC-PV or iC-MV) is stored in EEPROM lo-
cations 0x00 - 0x0F. Refer to the datasheet of the ap-
propriate device for details.
iC-MHM configuration data in RAM addresses 0x00 -
0x0C is stored in EEPROM locations 0x10 - 0x1C. This
data includes the checksum stored at address 0x0C.
Refer to REGISTER MAP: RAM on page 16 for more
information.
iC-MHM absolute position offset values stored in RAM
addresses 0x0D - 0x13 are stored in EEPROM loca-
tions 0x1D - 0x23. This data includes the checksum
stored at address 0x23. Refer to REGISTER MAP:
RAM on page 16 for more information.
At power up, the iC-MHM configuration in EEPROM
addresses 0x10 - 0x23 is copied onto iC-MHM RAM
addresses 0x00 - 0x13.
EEPROM addresses above 0x3F are used by the BiSS
interface for storage of the position preset value and
user data. Refer to SERIAL INTERFACE: BiSS Mode
on page 37 for more information. The complete register
layout of the EEPROM is shown in REGISTER MAP:
EEPROM on page 35.
When writing to the EEPROM, a wait time of at least
4 ms must be allowed after each write. Alternatively, the
same byte can be read back after it is written and the
values compared. This comparison will fail if the EEP-
ROM is busy with its internal write procedure. Several
attempts may be required for the read value to equal
the written value before the next location can be written.