IC-MHM Datasheet, PDF (49/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
Rev D1, Page 49/63
occurs during a read status command (invalid address,
invalid data, etc.), the fail bit in the SPI status byte is
set, the address counter is no longer incremented, and
the data returned is invalid. Refer to Table 96 on page
50 for more information.
Figure 31: Register Write (Continuous)
The master transmits the write register opcode (0xCF)
followed by the starting address of the block of ad-
dresses to write (ADR), followed by the data to write to
the register at address ADR (DATA1), the data to write
to the address at ADR + 1 (DATA2), etc. on MOSI. The
iC-MHM immediately outputs the MOSI bits on MISO.
Data continues to be written to subsequent registers as
long as NCS stays active (low).
The register data channel must be activated (RAC-
TIVE = 1) for proper operation of this command, other-
wise the error bit in the SPI status byte is set. If an error
occurs during a register write (invalid address, invalid
data, etc.), the fail bit in the SPI status byte is set, the
address counter is no longer incremented, and the data
in not written. Refer to Table 96 on page 50 for more
information.
Read Status
The Read Status command directly reads the iC-MHM
status registers at address 0x70 - 0x73.
Write Instruction
The Write Instruction command writes values directly
to the iC-MHM instruction registers.
Figure 33: Write Instruction
The master transmits the Write Instruction opcode
(0xD9) on MOSI, followed by the data for the instruc-
tion registers starting at address 0x74 (INST1). The
iC-MHM immediately outputs the opcode and data on
MISO. As long as NCS stays active (low), data for the
next instruction register can be written (INST2). Data
for subsequent registers can be written as long as NCS
remains low. Refer to INSTRUCTION REGISTERS on
page 32 for more information.
This command is similar to the Write Register (Continu-
ous) command except that the starting address of the
instruction registers does not need to be specified.
Figure 32: Read Status
The master transmits the Read Status opcode (0x9C)
on MOSI. The iC-MHM immediately outputs the opcode
on MISO followed by the data from the status registers
starting at address 0x70 (STAT1). As long as NCS
stays active (low), data from the the next status register
is then output (STAT2). Data from subsequent registers
continues to be output as long as NCS remains low.
Refer to STATUS REGISTERS on page 30 for more
information.
This command is similar to the Read Register (Continu-
ous) command except that the starting address of the
status registers does not need to be specified.
The register data channel must be activated (RAC-
TIVE = 1) for proper operation of this command, other-
wise the error bit in the SPI status byte is set. If an error
The register data channel must be activated (RAC-
TIVE = 1) for proper operation of this command, oth-
erwise the error bit in the SPI status byte is set. If an
error occurs during a Write Instruction command (in-
valid address, invalid data, etc.), the fail bit in the SPI
Status byte is set, the address counter is no longer
incremented, and the instruction register is not written.
Refer to Table 96 on page 50 for more information.
Register Read (Single)
The Register Read command (0x97) reads data from
the register at the specified address. Refer to REGIS-
TER MAP: RAM on page 16 for register addresses.
In operation, the SPI master transmits the read register
opcode (0x79) followed by the address of the register
to read on MOSI. The iC-MHM immediately outputs the
opcode and address on MISO followed by the data from
the register at the specified address.
The register data channel must be activated (RAC-
TIVE = 1) for proper operation of this command, other-
wise the error bit in the SPI status byte is set. If an error
occurs during a register read (invalid address, invalid