IC-MHM Datasheet, PDF (46/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
SERIAL INTERFACE: SPI Mode
Rev D1, Page 46/63
General Protocol Description
The SPI interface in the iC-MHM is a SPI slave and
supports SPI modes 0 and 3, meaning that the idle
state of SCLK (MA) can be 0 or 1. Data is always ac-
cepted on the rising edge of SCLK and the idle state of
MISO (SLO) is 1. As shown in Figure 27, a falling edge
on NCS initiates an SPI transaction causing the MOSI
signal (SLI) to be fed through to MISO (SLO). Data is
sent byte by byte with the MSB (most significant bit)
first.
NCS
SCLK (MA): MODE 0
SCLK (MA): MODE 3
MOSI (SLI)
MISO (SLO)
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Figure 27: SPI Transmission
When SPI mode is not selected (NCS high), the serial
interface is in BiSS or SSI mode (depending on the
setting of parameter ENSSI) and MISO is driven high.
To prevent any side effects it is recommended to dis-
able BiSS by setting parameter DISBiSS = 1. Further
with this configuration MISO is in tristate (high Z) and
clock signals on MA are ignored when NCS is not ac-
tive. This allows bussing multiple iC-MHMs to a single
SPI master. Refer to Bussing and Chaining Multiple
iC-MHMs on page 50 for more information.
OPCODE
Code
0xB0
0xA6
0x8A
0xCF
0x9C
0xD9
0x97
0xD2
0xAD
Description
Activate
Position Read
Register Read (Continuous)
Register Write (Continuous)
Read Status
Write Instruction
Register Read (Single)
Register Write (Single)
Read Register Status/Data
Table 90: Operation Codes
These opcodes are explained following.
DISBISS
Value
0
1
Addr. 0x07; bit 5
Description
BiSS Enabled
MISO (SLO) Driven High When NCS Inactive
BiSS Disabled
MISO (SLO) in Tristate (High Z) When NCS Inactive
Table 89: Disable BiSS Interface
Activate
The Activate opcode (0xB0) turns the register and sen-
sor data channels in the iC-MHM on and off individually.
This command causes the iC-MHM to reset its RAC-
TIVE (register data channel) and PACTIVE (sensor data
channel) bits, turning both channels off, and resets the
Fail, Valid, Busy, and Dismiss bits in the SPI status
byte (refer to Table 96 on page 50). The RACTIVE
and PACTIVE bits in the data byte following the op-
code then activate one or both channels for subsequent
transactions.
Opcodes
Each SPI transaction begins with a 1-byte opcode (op-
eration code or command) sent by the SPI master. As
shown in Table 90, the opcode determines whether
configuration (register) or sensor (position) data is ac-
cessed.
RACTIVE
Code
0
1
Note
Description
Register communication deactivated
Register communication activated*)
*) default after startup
Table 91: RACTIVE