IC-MHM Datasheet, PDF (50/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
Rev D1, Page 50/63
data, etc.), the fail bit in the SPI status byte is set and
the data returned is invalid. Refer to Table 96 on page
50 for more information.
Status bits are updated with every register access, ex-
cept error, which indicates the status of the last com-
mand (opcode).
Register Write (Single)
The Register Write command (0xD2) writes data to the
register at the specified address. Refer to REGISTER
MAP: RAM on page 16 for register addresses.
In operation, the master transmits the write register op-
code (0xD2) followed by the address of the register to
write, followed by the data to write to the register on
MOSI. The iC-MHM immediately outputs the MOSI bits
on MISO.
If the Read Register Status command immediately fol-
lows a Read Register command, the DATA byte re-
turned by the Read Register Status command is the
same as that returned by the previous Read Register
command. If the Read Register Status command im-
mediately follows a Write Register command, the DATA
byte returned by the Read Register Status command is
the data that was written by the previous Write Register
command. With all other commands, the DATA byte is
not defined.
The register data channel must be activated (RAC-
TIVE = 1) for proper operation of this command, other-
wise the Error bit in the SPI Status byte is set. If an error
occurs during a register write (invalid address, invalid
data, etc.), the Fail bit in the SPI Status byte is set and
the data in not written. Refer to Table 96 on page 50 for
more information.
Bussing and Chaining Multiple iC-MHMs
Multiple iC-MHMs can be bussed or chained to a sin-
gle SPI master. Figure 35 shows two iC-MHMs in a
chained configuration.
Read Register Status/Data
The Read Register Status/Data command (0xAD) re-
turns the SPI status byte which indicates the status of
the last register transaction or data transmission.
1
NCS
SCLK
MOSI
OP ADR
+
MISO
OP
ADR
2
OP
OP STATUS DATA
Figure 35: Chaining Multiple iC-MHMs
8 cycles
Figure 34: Read Register (single): set the read
address (1) + command Register
Status/Data to read-out data (2)
As shown in Figure 34, the SPI status byte is returned
immediately following the opcode (STATUS) and is fol-
lowed by a data byte (DATA).
In this configuration, the MISO (SLO) output of each
iC-MHM is chained to the MOSI (SLI) input of the next
device in the chain. The SPI master must activate the
desired channel(s) in a specific slave device to com-
municate with it. The required RACTIVE and PACTIVE
bits for each slave are packed into the bytes following
the Activate opcode, as shown in Figure 36.
Table 96 shows the SPI status byte bits.
STATUS
Bit
7
6:4
3
2
1
0
Name
Error
-
Dismiss
Fail
Busy
Valid
Description
Invalid opcode
Reserved
Illegal Address
Data request failed
Slave busy
Data valid
Table 96: SPI Status Byte
Figure 36: Activate Command For Multiple Slaves
For example, Figure 37 shows MOSI and MISO for an
Activate command for one and two chained slaves.