IC-MHM Datasheet, PDF (3/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
CONTENTS
Rev D1, Page 3/63
PACKAGING INFORMATION
PIN CONFIGURATION QFN28-5x5 . . . . .
PACKAGE DIMENSIONS . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
5
Gain . . . . . . . . . . . . . . . . . . . . . . . 32
5
6 ^{TEST MODE}
33
7 ^{EEPROM AND I2C INTERFACE (Multi-master) 33}
Basic interface features . . . . . . . . . . . . 33
7
EEPROM device requirements . . . . . . . . 33
ELECTRICAL CHARACTERISTICS
8 REGISTER MAP: EEPROM
35
CHARACTERISTICS: Diagrams . . . . . . . 11
SERIAL INTERFACE: General
36
OPERATING REQUIREMENTS
11
Multiturn Interface . . . . . . . . . . . . . . . 11 ^{SERIAL INTERFACE: BiSS Mode}
37
Serial Interface (BiSS, SSI) . . . . . . . . . . 12
BiSS Single Cycle Data (SCD) . . . . . . . . 37
Serial Interface (SPI) . . . . . . . . . . . . . . 13
Adaptive Timeout . . . . . . . . . . . . . . . . 38
BiSS Control Communication . . . . . . . . . 39
REVERSE POLARITY PROTECTION
14
BiSS Register Access . . . . . . . . . . . . . 41
OVERVOLTAGE PROTECTION
CONFIGURATION PARAMETERS
14 SERIAL INTERFACE: SSI Mode
43
Standard SSI Protocol . . . . . . . . . . . . . 44
14
Extended SSI Protocol . . . . . . . . . . . . . 44
REGISTER MAP: RAM
16 _{SERIAL INTERFACE: SPI Mode}
46
HALL SENSORS: Principle of Operation
17
General Protocol Description . . . . . . . . . 46
Bussing and Chaining Multiple iC-MHMs . . . 50
SIGNAL CONDITIONING
18
CONFIGURATION
52
INTERPOLATOR
MULTITURN INTERFACE
21
Initial Configuration . . . . . . . . . . . . . . . 52
BiSS Mode Configuration . . . . . . . . . . . 52
23
Example of CRC Calculation Routine . . . . 53
DIGITAL I/O PORT
SPI Mode Configuration . . . . . . . . . . . . 53
26
Digital I/O 1 (P1) . . . . . . . . . . . . . . . . 26 _CALIBRATION
54
Digital I/O 2 (P2) . . . . . . . . . . . . . . . . 26
Gain Calibration . . . . . . . . . . . . . . . . 54
Digital I/O 3 (P3) . . . . . . . . . . . . . . . . 27
Centering the Magnet . . . . . . . . . . . . . 54
Digital I/O 0 (MDI and MCL) . . . . . . . . . . 28
Offset and Gain Correction Cosine Calibration 54
Incremental Quadrature (ABZ) Outputs . . . 29
Harmonic Calibration . . . . . . . . . . . . . . 54
STATUS REGISTERS
30 _{POSITION OFFSET AND PRESET (Zero}
Error . . . . . . . . . . . . . . . . . . . . . . . 30
Position)
55
Digital I/O Pin States . . . . . . . . . . . . . . 30
Preset Position . . . . . . . . . . . . . . . . . 55
GAIN . . . . . . . . . . . . . . . . . . . . . . 31
Position Preset Sequence . . . . . . . . . . . 55
Chip Release (CHIP_REL) . . . . . . . . . . 31
STARTUP AND OPERATION
57
INSTRUCTION REGISTERS
32
Startup . . . . . . . . . . . . . . . . . . . . . 57
Reset and Preset . . . . . . . . . . . . . . . . 32
Operation . . . . . . . . . . . . . . . . . . . . 58
Discrete Output . . . . . . . . . . . . . . . . . 32
Position Preset Sequence . . . . . . . . . . . 58