IC-MHM Datasheet, PDF (15/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
CONFIGURATION PARAMETERS
Rev D1, Page 15/63
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 18
GAINR:
GAINF:
ENAC:
VOSS:
VOSC:
GCC:
ENF:
HARMCAL:
Coarse Gain Range
Fine Gain
Automatic Amplitude Control Enable
Offset Correction Sine
Offset Correction Cosine
Gain Correction Cosine
Filter Enable
Harmonic Calibration
Interpolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21
RESO_ST:
AVGFILT:
DIR:
HYS:
TLF:
Singleturn Resolution
Averaging Filter
Code Direction
Hysteresis
Tracking Loop Frequency
Multiturn Interface . . . . . . . . . . . . . . . . . . . . . . . . Page 23
CF_MTI:
RESO_MT:
SBL_MTI:
EBL_MTI:
GET_MTI:
Clock Frequency
Multiturn Resolution
Multiturn Synchronization Bits
Multiturn Error Bits
Multiturn Interface Feedthrough
INSPROT: Instruction Register Protection
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 33
TEST:
Test Mode
Serial Interface: General . . . . . . . . . . . . . . . . . . Page 36
RTX_MODE: Transceiver Configuration
Serial Interface: BiSS Mode . . . . . . . . . . . . . . Page 37
ENSSI:
DISBISS:
MT12:
ENLC:
CRCS:
NTOA:
ENCMD01:
ENCMD2:
ENCMD3:
REGPROT:
INSPROT:
I2CDEV:
BSEL:
BiSS/SSI Protocol Selection
Disable BiSS Interface
Multiturn Bit Length
Sign-of-Life Counter Enable
CRC Start Value
Adaptive Timeout
BiSS Command 01 Enable
BiSS Command 2 Enable
BiSS Command 3 Enable
BiSS Register Protection
Instruction Register Protection
I²C Device ID
Bank Selection
Digital I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 26
CFG_IOP:
F_IO0:
F_IO1:
F_IO2:
F_IO3:
S_IO0:
S_IO1:
S_IO2:
S_IO3:
PRES_IO1:
DIR_IO2:
ENCMD2:
I/O Port Function
MCL Force Level (pin 10)
P1 Force Level (pin 5)
P2 Force Level (pin 6)
P3 Force Level (pin 7)
MDI Sense Level (pin 11)
P1 Sense Level (pin 5)
P2 Sense Level (pin 6)
P3 Sense Level (pin 7)
Enable Preset Input P1
Enable Code Direction Input P2
BiSS Command 2 Enable
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Page 30
ERR_CFG:
ERR_OFFS:
ERR_POS:
ERR_EXT:
ERR_AMIN:
ERR_AMAX:
ERR_MTI:
ERR_MT:
GAIN:
CHIP_REL:
Configuration Data CRC Error
Output Offset CRC Error
Absolute Position Error
External Error
Minimum Amplitude Error
Maximum Amplitude Error
Multiturn Interface Error
Multiturn Position Error
Gain Control Value
Chip Release
Instruction Registers . . . . . . . . . . . . . . . . . . . . . Page 32
Serial Interface: SSI Mode . . . . . . . . . . . . . . . . Page 44
ENSSI:
DISBISS:
EXT_SSI:
BIN_SSI:
MT12:
NTOA:
ENLC:
BiSS/SSI Protocol Selection
Disable BiSS Interface
SSI Protocol
SSI Numeric Format (Gray or binary)
Multiturn Bit Length
Adaptive Timeout
Sign-of-Life Counter Enable
Serial Interface: SPI Mode . . . . . . . . . . . . . . . . Page 46
DISBISS:
Disable BiSS Interface
RESO_MT: Multiturn Resolution (SPI)
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 52
CRC_CFG: Configuration Data Checksum
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 54
CIBM:
Bias Current Calibration
Position Offset and Preset . . . . . . . . . . . . . . . . Page 55
OFFS_MT:
OFFS_ST:
CRC_OFFS:
PSET_MT:
PSET_ST:
CRC_PSET:
Multiturn Offset
Singleturn Offset
Position Offset Checksum
Multiturn Preset Position
Singleturn Preset Position
Preset Position Checksum