IC-MHM Datasheet, PDF (48/63 Pages) IC-Haus GmbH – 14-BIT ABSOLUTE ANGLE HALL ENCODER

iC-MHM
14-BIT ABSOLUTE ANGLE HALL ENCODER
RESO_MT
Value
0
1
2
3
4
5
6
7
Address 0x01; bits 2:0
Resolution (Bits)
0
Not Permissible
8
Not Permissible
16
Not Permissible
24
32
Byte Length
0
-
1
-
2
-
3
4
Table 94: Multiturn Resolution (SPI)
Rev D1, Page 48/63
Register Data
Address Content
0x00 ...
0x13
RAM
0x14 ...
0x6F
not used
0x70 ...
0x73
Status Messages
0x74 ...
0x77
Instruction Register
Table 95: Register Access
Only certain multiturn resolutions can by used in SPI
mode, as shown above. In all cases, the number of bits
supplied by the external multiturn counter must match
the RESO_MT value. Refer to MULTITURN INTER-
FACE on page 23 for more information. If the multiturn
counter is not needed, set RESO_MT = 0.
Register Read (Continuous)
The Register Read (Continuous) command (0x8A)
reads data from a contiguous block of one or more
RAM addresses starting at a specified address.
Singleturn position (angle) is always transmitted using
two bytes. If the interpolator resolution as set by pa-
rameter RESO_ST is less than 16 bits, the singleturn
position value is left-justified in the singleturn position
field and the unused LSBs are set to zero.
Figure 30: Register Read (Continuous)
For example, if RESO_ST = 6, the singleturn position
(angle) is a 10-bit value in a 16-bit field. In this case,
bits 15:6 contain the singleturn position while bits 5:0
are zero. Refer to INTERPOLATOR on page 21 for
more information on RESO_ST.
The active-low error bit, nERR, is activated when any
of the error bits in the error status register is active.
Refer to STATUS REGISTERS on page 30 for more
information.
The master transmits the read register opcode (0x8A)
followed by the starting address of the block of ad-
dresses to read (ADR) on MOSI. The iC-MHM immedi-
ately outputs the opcode and address on MISO followed
by the data from the register at address ADR (DATA1).
As long as NCS stays active (low), data from the the
next register (address ADR + 1) is then output (DATA2).
Data from subsequent registers continues to be output
as long as NCS remains low.
The active-low warning bit, nWARN, is activated if mag-
net rotation speed is excessive. Refer to INTERPO-
LATOR on page 21 for more information on maximum
rotation speeds.
Register Access
Table 95 shows the register mapping used for SPI.
The register data channel must be activated (RAC-
TIVE = 1) for proper operation of this command, other-
wise the error bit in the SPI status byte is set. If an error
occurs during a register read (invalid address, invalid
data, etc.), the fail bit in the SPI status byte is set, the
address counter is no longer incremented, and the data
returned is invalid. Refer to Table 96 on page 50 for
more information.
Note: An access to an external EEPROM is not pos-
sible. Using OPCODEs Register Read (Single) and
Register Write (Single) is not recommended.
Register Write (Continuous)
The Register Write (Continuous) command (0xCF)
writes data to a contiguous block of one or more RAM
addresses starting at a specified address.