IC-MU_13 Datasheet, PDF (40/59 Pages) IC-Haus GmbH – OFF-AXIS NONIUS ENCODER WITH INTEGRATED HALL SENSORS

iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
preliminary
Rev B1, Page 40/59
Construction of a Multiturn system with two iC-MU
A 3 Track nonius system can be build using two iC-MU.
The singleturn iC-MU (1) can be configured to interpret
3, 4, 5, or 6 bits of the read multiturn data as singleturn
data (ST) (see Table 56). The output through the in-
cremental interface of iC-MU (1) is then absolute with
this additional information.
MPC
(2) (1)
0x7 0x4
0x8 0x4
0x9 0x5
0xA 0x5
0xB 0x6
0xC 0x6
Periods/revolution
Master Segm. Nonius
128 120 127
256 240 255
512 496 511
1024 992 1023
2048 2016 2047
4096 4032 4095
ST Periods [Bit]
from MT(2) from ST(1)
3
4
4
4
4
5
5
5
5
6
6
6
Table 63: Settings for a 3-track nonius system using 2
iC-MU
The construction of such a system is shown as an ex-
ample in Figure 38 and the configuration in Table 62.
iC-MU
(2)
iC-MU
(1)
nonius 1023
master 1024
segment 992
Permissible Max. phase deviation
Periods/revolution
[given in degree per signalperiod of 360°]
Master Segm. Nonius Master ↔ Segm. Master ↔ Non.*)
(1)
(2)
128 120 127 +/-9.84°
+/-19.68°
256 240 255 +/-9.84°
+/-9.84°
512 496 511 +/-4.92°
+/-9.84°
1024 992 1023 +/-4.92°
+/-4.92°
2048 2016 2047 +/-2.46°
+/-4.92°
4096 4032 4095 +/-2.46°
+/-2.46°
Note *) with SBL_MT=0x3
Master
SL
MA
Table 64: Tolerable phase deviation for the master ver-
sus the nonius or segment track of a 3-track
nonius system (with reference to 360°, elec-
trical)
Figure 38: 3-track nonius with 2 iC-MU
Figure 39 shows the principle of the synchronisation of
the data from iC-MU (2) to iC-MU (1).
iC-MU (1): singleturn
Parameter Value
MPC
0x5
MODE_MT 0x5
SBL_MT 0x3
iC-MU (2): multiturn
Parameter Value
MPC
0xA
MODE_MT 0x0
MODE_ST 0x0
OUT_MSB 0xA
OUT_LSB 0xF
Description
5 Bit ST periods
5 Bit ST periods via multiturn
4 Bit synchronisation of read multiturn
data
Description
10 Bit periods
no additional multiturn data
output of internal absolute data
MSB output configuration
9 Bit output data while having 10 Bit
periods
LSB output configuration
9 Bit output data while having 10 Bit
periods
Bits of Multiturn MU (2)
ϕm - ϕn
SYNC BITS
ϕm - ϕs
CORRECTION
SYNC BITS
ϕm
CORRECTION
MPC (2)
MPC (1)
12 Bit
ϕm
ϕabsolut
CNT_PERIOD
+
MSB
INTERNAL
LSB _{W ORD}
Figure 39: Principle of the synchronisation of a 3-
track nonius system using 2 iC-MU with-
out further multiturn data
Table 62: Configuration example for the 3-track nonius
system of Fig.38
Table 63 shows the possible settings for a 3-track no-
nius systems with 2 iC-MU and the resulting period-
s/revolution of the tracks. The maximum phase devia-
tion of the tracks is summarized in Table 64.
To facilitate the initial configuration of an iC-MU as a
SSI multiturn device the command SWITCH can be
used (see page 52). The singleturn iC-MU (1) in
Figure 38 has to enable the direct communication to
the multiturn sensor by setting GET_MT to 1. The
configuration of iC-MU (2) can take place using the
BiSS protocol. After the configuration of the exter-
nal multiturn MODEA_NEW and RPL_NEW are used