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IC-MU_13 Datasheet, PDF (23/59 Pages) IC-Haus GmbH – OFF-AXIS NONIUS ENCODER WITH INTEGRATED HALL SENSORS
iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
preliminary
Startup behavior
After switching on the power (power-on reset) iC-MU
reads the configuration data out from the EEPROM. If
an error occurs during the EEPROM data readout (a
CRC error or communication fault with the EEPROM),
the current read-in is aborted and restarted. Following
a third faulty attempt the read-in process is terminated
and the internal iC-MU configuration register initialized
as in Tab. 27. The addresses are referenced to the
register allocation for an register access through the
serial interface s. p. 45.
N.B.: After the third faulty attempt to read-in the con-
figuration data from the EEPROM the default value of
MODEA is set to BiSS or SPI depending on the logic
level at pin PA0 (PA0=0 → BiSS, PA0=1 → SPI).
The amplitude control is started after the read-in of the
EEPROM. To determine the absolute position a nonius
calculation is started. An external multiturn is read-in if
configured. If there is an error the multiturn read-in is
repeated until no multiturn error occurs. The Statusbit
MT_ERR is set in this case, register communication
is possible. The ABZ/UVW-converter is only started
if there was no CRC_ERR, EPR_ERR, MT_ERR or
MT_CTR error during startup. The startup behaviour
is described in picture 11.
Rev B1, Page 23/59
Default values
Bank
Addr.
(serial
access)
value
Meaning
0
0x05
0x88
Amplitude control active
(ENAC=1), CIBM = 0%
0
0x0B
0x02
PA0=0 → BiSS interface
(MODEA=0x2),
ABZ Incremental
(MODEB=0x0)
0
0x00
PA0=1 → SPI interface
(MODEA=0x0),
ABZ Incremental
(MODEB=0x0)
0
0x0E
0x06
FILTER activated
0
0x0F
0x05
32 pole pairs master
track
0
0x10
0x00
no Multiturn,
Noniuscheck active
0
0x11
0xA5
5 bit Noniusinformation,
5 Zeros added
0
0x12
0x00
output with max.
resolution
0
0x13
0xFF
resolution 16384 edges
0
0x14
0x0F
0
0x15
0x13
up to 12000 rpm
(SS_AB=0x1),
266ns minimum edge
distance
0
0x16
0x10
90° Index, 0.08°
Hysteresis
0
0x17
0x02
1 pole pair Polpaar
commutation
-
0x78
0x4D
M
-
0x79
0x55
U
-
0x7A
HARD_REV s. Tab. 87
-
0x7E
0x69
i
-
0x7F
0x43
C
Notes:
all other registers are preset with 0
Register assignment for register access through
serial interface s. S. 45
Table 27: Default configuration without the EEPROM