IC-MU_13 Datasheet, PDF (28/59 Pages) IC-Haus GmbH – OFF-AXIS NONIUS ENCODER WITH INTEGRATED HALL SENSORS

iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
preliminary
BiSS C interface
Rev B1, Page 28/59
0 0 ERR WRN
Zero bits
busy
OUT
cycle
MODEA
Code
0x2
Figure 13: Example of BiSS line signals
Description
BiSS-C
Table 36: MODEA: BiSS
In BiSS protocol iC-MU uses fixed CRC polynomi-
als, see Table 37. The singlecycle data (SCD), i.e.
the primary data which is newly generated and com-
pletely transmitted in each cycle, contains the position
data (optional multiturn + singleturn) and the error and
warning bit. The CRC value is output inverted.
The BiSS C interface has an adaptive sensor data
timeout. Data is output in binary form. The error and
warning bit is low active. Transmission of sensor and
register data is implemented. iC-MU needs no pro-
cessing time therefore t_busy is one master clock cycle.
For further information regarding the BiSS-C-protocol
visit www.biss-interface.com.
data-
channel*)
SCD
(sensor)
CDM, CDS
(register)
Note:
CRC
HEX Code
0x43
0x13
Polynomial
x⁶+x¹+x⁰
x⁴+x¹+x⁰
*) explanation s. BiSS-C specification
Table 37: BiSS CRC polynomials