IC-MU_13 Datasheet, PDF (32/59 Pages) IC-Haus GmbH – OFF-AXIS NONIUS ENCODER WITH INTEGRATED HALL SENSORS

iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
preliminary
NCS
SCLK
MOSI
MISO
OP
RAPA 0-3 RAPA 4-7
...
OP
8 cycles
Figure 17: Set ACTIVATE: RACTIVE/PACTIVE
(several slaves)
The ACTIVATE command resets the bits FAIL, VALID,
BUSY, and DISMISS in the SPI-STATUS byte (see Ta-
ble 46).
RACTIVE
Code
0
1
Note
Description
Register communication deactivated
Register communication activated*)
*) default after startup
Table 43: RACTIVE
NCS
SCLK
MOSI
MISO
Rev B1, Page 32/59
OP
1 0 0 0 0 0 RA0 PA0
OP
00
100000
MOSI
MISO
OP
1 0 0 0 RA0 PA0 RA1 PA1
OP
00001000
8 cycles
RACTIVE/PACTIVE-vector
Figure 18: Set ACTIVATE: RACTIVE/PACTIVE
(Example with one and two slaves)
MISO
SCLK
NCS
SPI
Master
MOSI
iC-MU
MOSI
MISO
(1)
iC-MU
MOSI
MISO
(0)
Figure 19: Example configuration with 2 Slaves
(daisy chained)
If RACTIVE is not set, on commands Read REGIS-
TER (single), Write REGISTER (single), REGISTER
status/data the ERROR bit is set in the SPI-STATUS
byte (see Table 46) to indicate that the command has
not been executed. At MISO the slave immediately
outputs the data transmitted by the master via MOSI.
PACTIVE
Code
0
1
Note
Description
Sensor data channel deactivated
Sensor data channel activated*)
*) default after startup
Table 44: PACTIVE
If PACTIVE is not set, on commands SDAD status and
SDAD transmission the ERROR bit is set in the SPI-
STATUS byte (see Table 46) to indicate that the com-
mand has not been executed. At MISO the slave im-
mediately outputs the data transmitted by the master
via MOSI.
SPI interface: Command SDAD transmission
iC-MU samples the actual converter values on the first
rising edge at SCLK, when NCS is at zero (REQ). Be-
cause iC-MU can output the sensor data (SD) immedi-
ately, the master can transmit the SDAD transmission
command directly. The sensor data shift register (the
size of which is 8 to 40 bits in multiples of 8 using iC-
MU) is switched and clocked out between MOSI and
MISO.
If invalid data is sampled in the shift register, the ER-
ROR bit is set in the SPI-STATUS byte (see Table 46)
and the output data bytes are set to zero.
REQ
NCS
SCLK
MOSI
OP
MISO
OP
SD1 SD2
...
8 cycles
Figure 20: SDAD transmission: read SD
If only one slave is connected up with one register and
one sensor data channel, it must be ensured that the
RACTIVE and PACTIVE bits come last in the data byte.
SPI interface: Command SDAD status
If the master does not know the processing time of the
connected slaves, it can request sensor data using the
command SDAD status. The command causes: