IC-MU_13 Datasheet, PDF (38/59 Pages) IC-Haus GmbH – OFF-AXIS NONIUS ENCODER WITH INTEGRATED HALL SENSORS

iC-MU OFF-AXIS NONIUS ENCODER
WITH INTEGRATED HALL SENSORS
preliminary
Rev B1, Page 38/59
MT INTERFACE
MTC
MTD
MSB
LSB
MODE_MT + SBL_MT + ESSI_MT
tout
Figure 33: Example of multiturn SSI line signals
Configuration of the Multiturn interface
MODE_MT(3:0) Addr. 0x10; bit 3:0
Code
Function
Code
Function
0x0
no external data 0x8
4 *) + 12 bit
0x1
1 *) bit
0x9
5 *) + 12 bit
0x2
2 *) bit
0xA
6 *) + 12 bit
0x3
3 *) bit
0xB
4 bit
0x4
4 *) bit
0xC
8 bit
0x5
5 *) bit
0xD
12 bit
0x6
6 *) bit
0xE
16 bit
0x7
3 *) + 12 bit
0xE
18 bit
Notes:
*) data interpreted as ST
If MPC ≥ 0x07 than MODE_MT has to be set to
0x0 or 0xD
iC-MU can read in and synchronize binary data from
an external SSI sensor through the serial multiturn in-
terface. On startup the first data value read in deter-
mines the start value of the internal period counter. Af-
ter startup the multiturn periods are counted internally
and output. If there is an error reading the multiturn
during startup, the read-in will be repeated.
Table 56: MT interface operating mode
For synchronization a synchronization bit length must
be set by SBL_MT. Synchronization takes place be-
tween the read external multiturn word and the internal
counted cycle data. Synchronization can take place
automatically within the relevant phase tolerances.
multiturn-
startup
read external
multiturn
serial-communication error? ^yes
no
sync to master track
set MT_ERR
proceed with
startup-sequence
SBL_MT(1:0)
Addr. 0x10; bit 5:4
Code
MT synchronisation
bitlength
synchronisation
tolerance (ST-resolution)
0x0
1 bit
± 90°
0x1
2 bit
± 90°
0x2
3 bit
± 135°
0x3
4 bit
± 157,5°
Table 57: MT synchronization bit length
Figure 35 shows the principle of a 2 bit MT synchro-
nization for ideal signals (without indication of synchro-
nization tolerance limits).
Figure 34: Error handling during startup
ST MSB -1
180° 270° ^{0° 90°} 180° 270° ^{0° 90°}
If the MT interface is not used (MODE_MT=0x0), the
internal 24-bit period counter can extend the singleturn
data output to include the counted multiturn cycles.
ST MSB
MT LSB -2
MT LSB -1
For exclusive multiturn systems a 4, 8, 12, 16 or 18-bit
multiturn data value can be read in (MODE_MT=0xB-
0xE). There is also the possibility to interpret a part
of the external multiturn data value as singleturn. For
further information see Construction of a Multiturn
system with two iC-MU S. 40.
MT LSB
multiturn
data output
°/ST
Figure 35: Principle of 2 bit MT synchronization