HMT164U6AFP6C-S6 Datasheet, PDF (47/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 11 — IDD Measurement Conditions for IDD6 and IDD6ET
Current
Name
Temperature
Auto Self Refresh (ASR) /
MR2 Bit A6
I_DD6
Self-Refresh Current
Normal Temperature Range
T_CASE = 0. 85 °C
Measurement Condition
T_CASE = 85 °C
Disabled / “0”
I_DD6ET
Self-Refresh Current
Extended Temperature Range ^a
T_CASE = 0. 95 °C
T_CASE = 95 °C
Disabled / “0”
Self Refresh Temperature
Range (SRT) /
MR2 Bit A7
Normal / “0”
Extended / “1”
CKE
LOW
LOW
External Clock
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
OFF; CK and CK at LOW
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
OFF; CK and CK at LOW
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
AL
n.a.
n.a.
CS
FLOATING
FLOATING
Command Inputs
(RAS, CAS, WE)
FLOATING
FLOATING
Row, Column Addresses
FLOATING
FLOATING
Bank Addresses
FLOATING
FLOATING
Data I/O
FLOATING
FLOATING
Output Buffer DQ,DQS
/ MR1 bit A12
off / 1
off / 1
ODT
/ MR1 bits [A6, A2]
disabled
/ [0,0]
disabled
/ [0,0]
Burst length
n.a.
n.a.
Active banks
all during self-refresh actions
all during self-refresh actions
Idle banks
all btw. Self-Refresh actions
all btw. Self-Refresh actions
Precharge Power Down Mode
n.a.
n.a.
/ MR0 bit A12
a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM
devices support the following options or requirements referred to in this material.
Rev. 0.1 / Dec 2008
47