HMT164U6AFP6C-S6 Datasheet, PDF (36/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 5 — IDD Measurement Conditions for IDD0 and IDD1
Current
I_DD0
I_DD1
Name
Operating Current 0
-> One Bank Activate
-> Precharge
Operating Current 1
-> One Bank Activate
-> Read
-> Precharge
Measurement Condition
Timing Diagram Example
Figure 1
CKE
HIGH
HIGH
External Clock
on
on
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
t_CKmin(IDD)
t_RCmin(IDD)
t_RASmin(IDD)
n.a.
n.a.
n.a.
t_CKmin(IDD)
t_RCmin(IDD)
t_RASmin(IDD)
t_RCDmin(IDD)
n.a.
CL(IDD)
AL
n.a.
0
CS
HIGH between. Activate and Precharge HIGH between Activate, Read and
Commands
Precharge
Command Inputs
SWITCHING as described in Table 2
SWITCHING as described in Table 2; only
(CS,RAS, CAS, WE)
only exceptions are Activate and
exceptions are Activate, Read and
Precharge commands; example of IDD0 Precharge commands; example of IDD1
pattern:
pattern:
A0DDDDDDDDDDDDDD P0
(DDR3-800: t_RAS = 37.5ns between
(A)ctivate and (P)recharge to bank 0;
A0DDDDR0DDDDDDDDD P0
(DDR3-800 -555: t_RCD = 12.5ns between
(A)ctivate and (R)ead to bank 0;
Definition of D and D: see Table 2
Definition of D and D: see Table 2)
Rev. 0.1 / Dec 2008
36