HMT164U6AFP6C-S6 Datasheet, PDF (42/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Current
I_DD4R
I_DD4W
Name
Operating Current
Burst Read
Operating Current
Burst Write
I_DD7
All Bank Interleave Read
Current
Measurement Condition
Timing Diagram
Example
Figure 3
CKE
HIGH
HIGH
HIGH
External Clock
on
on
on
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
CL(IDD)
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
CL(IDD)
t_CKmin(IDD)
t_RCmin(IDD)
t_RASmin(IDD)
t_RCDmin(IDD)
t_RRDmin(IDD)
CL(IDD)
AL
0
0
t_RCDmin - 1 t_CK
CS
HIGH btw. valid cmds
HIGH btw. valid cmds
HIGH btw. valid cmds
Command Inputs (CS,
RAS, CAS, WE)
SWITCHING as described in
Table 2; exceptions are Read
commands => IDD4R
Pattern:
SWITCHING as described in
Table 2; exceptions are Write
commands => IDD4W
Pattern:
For patterns see Table 9
R0DDDR1DDDR2DDDR3.DD
D R4.....
Rx = Read from bank x;
Definition of D and D: see
Table 2
W0DDDW1DDDW2DDDW3
DDD W4...
Wx = Write to bank x;
Definition of D and D: see
Table 2
Rev. 0.1 / Dec 2008
42