HMT164U6AFP6C-S6 Datasheet, PDF (37/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 5 — IDD Measurement Conditions for IDD0 and IDD1
Current
Name
I_DD0
Operating Current 0
-> One Bank Activate
-> Precharge
I_DD1
Operating Current 1
-> One Bank Activate
-> Read
-> Precharge
Row, Column Addresses
Row addresses SWITCHING as described Row addresses SWITCHING as described
in Table 2;
in Table 2;
Bank Addresses
Data I/O
Address Input A10 must be LOW all the
time!
bank address is fixed (bank 0)
SWITCHING as described in Table 3
Output Buffer DQ,DQS
off / 1
/ MR1 bit A12
ODT
disabled
/ MR1 bits [A6, A2]
/ [0,0]
Burst length
n.a.
Active banks
one
ACT-PRE loop
Idle banks
all other
Precharge Power Down Mode / n.a.
Mode Register Bit 12
Address Input A10 must be LOW all the
time!
bank address is fixed (bank 0)
Read Data: output data switches every
clock, which means that Read data is
stable during one clock cycle.
To achieve Iout = 0mA, the output buffer
should be switched off by MR1 Bit A12 set
to “1”.
When there is no read data burst from
DRAM, the DQ I/O should be FLOATING.
off / 1
disabled
/ [0,0]
8 fixed / MR0 Bits [A1, A0] = {0,0}
one
ACT-RD-PRE loop
all other
n.a.
Rev. 0.1 / Dec 2008
37