HMT164U6AFP6C-S6 Datasheet, PDF (43/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7
Current
I_DD4R
I_DD4W
Name
Operating Current
Burst Read
Operating Current
Burst Write
I_DD7
All Bank Interleave Read
Current
column addresses
column addresses
Row, Column
Addresses
SWITCHING as described in
Table 2;
Address Input A10 must be
LOW all the time!
SWITCHING as described in
Table 2;
Address Input A10 must be
LOW all the time!
STABLE during DESELECTs
Bank Addresses
bank address cycling (0 -> 1 -
bank address cycling (0 -> 1 - bank address cycling (0 -> 1 -
> 2 -> 3...), see pattern in
> 2 -> 3...)
> 2 -> 3...)
Table 9
DQ I/O
Seamless Read Data Burst
(BL8): output data switches
every clock, which means that
Read data is stable during one
clock cycle.
Seamless Write Data Burst
(BL8): input data switches
every clock, which means that
Write data is stable during one
clock cycle.
Read Data (BL8): output data
switches every clock, which
means that Read data is
stable during one clock cycle.
To achieve Iout = 0mA the
output buffer should be
switched off by MR1 Bit A12
set to “1”.
DM is low all the time.
To achieve Iout = 0mA the
output buffer should be
switched off by MR1 Bit A12
set to “1”.
Output Buffer
DQ,DQS
off / 1
off / 1
off / 1
/ MR1 bit A12
ODT
disabled
disabled
disabled
/ MR1 bits [A6, A2]
/ [0,0]
/ [0,0]
/ [0,0]
Burst length
8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] =
{0,0}
{0,0}
{0,0}
Active banks
all
all
all, rotational
Idle banks
none
none
none
Precharge Power
Down Mode /
n.a.
n.a.
n.a.
Mode Register Bit
Rev. 0.1 / Dec 2008
43