HMT164U6AFP6C-S6 Datasheet, PDF (41/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 7 — IDD Measurement Conditions for IDD3N and IDD3P(fast exit)
Current
Name
I_DD3N
Active Standby Current
I_DD3P
Active Power-Down Current^a
Always Fast Exit
Measurement Condition
Timing Diagram Example
Figure 2
CKE
HIGH
LOW
External Clock
on
on
t_CK
t_RC
t_RAS
t_RCD
t_RRD
CL
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
t_CKmin(IDD)
n.a.
n.a.
n.a.
n.a.
n.a.
AL
n.a.
n.a.
CS
HIGH
STABLE
Addr. and cmd Inputs
SWITCHING as described in Table 2
STABLE
Data inputs
SWITCHING as described in Table 3
FLOATING
Output Buffer DQ,DQS
/ MR1 bit A12
off / 1
off / 1
ODT
disabled
disabled
/ MR1 bits [A6, A2]
/ [0,0]
/ [0,0]
Burst length
n.a.
n.a.
Active banks
all
all
Idle banks
none
none
Precharge Power Down Mode /
n.a. (Active Power Down Mode is always
Mode Register Bit ^a
n.a.
“Fast Exit” with DLL on
a. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active
power down. Instead bit 12 will be used to switch between two different precharge power down modes.
Rev. 0.1 / Dec 2008
41