HMT164U6AFP6C-S6 Datasheet, PDF (34/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 2 — Definition of SWITCHING for Address and Command Input Signals
SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as:
Address
(row, column):
If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change
then to the opposite value
(e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax.....
please see each IDDx definition for details
Bank address:
If not otherwise mentioned the bank addresses should be switched like the row/column
addresses - please see each IDDx definition for details
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH}
Command
(CS, RAS, CAS, WE):
Define Command Background Pattern = D D D D D D D D D D D D...
If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background
Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary
command.
See each IDDx definition for details and figures 1,2,3 as examples.
Table 3 — Definition of SWITCHING for Data (DQ)
SWITCHING for Data (DQ) is defined as
Data (DQ)
Data DQ is changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals, which means that data DQ is stable during one clock; see each IDDx
definition for exceptions from this rule and for further details.
See figures 1,2,3 as examples.
Data Masking (DM) NO Switching; DM must be driven LOW all the time
Rev. 0.1 / Dec 2008
34