HMT164U6AFP6C-S6 Datasheet, PDF (38/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
T0
T1
T2
T3 T4
T5 T6
T7 T8
T9 T10
T12
T14
T16
T18
CK
BA[2:0]
000
ADDR_a[9:0]
000
3FF
000
3FF
000
3F
ADDR_b[10]
ADDR_c[12:11]
00
11
00
11
00
CS
RAS
CAS
WE
CMD
ACT D D# D# D RD D# D# D D D# D# D D D# PRE D D D#
DQ
00110011
DM
IDD1 Measurment Loop
< Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer
should be switched off (per MR1 Bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split into 3
parts.
a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different
Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off
(slow exit, bit 12 = 0).
b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set,
Enter - Self Refresh
Rev. 0.1 / Dec 2008
38