HMT164U6AFP6C-S6 Datasheet, PDF (39/57 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT164U6AFP(R)6C
HMT112U6(7)AFP(R)8C
HMT125U6(7)AFP(R)8C
Table 6 — IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q
Current
I_DD2N
I_DD2P(1) ^a
I_DD2P(0)
I_DD2Q
Name
Precharge Standby
Current
Precharge Power
Down Current
Fast Exit -
MRS A12 Bit = 1
Precharge Power
Down Current
Slow Exit -
MRS A12 Bit = 0
Precharge Quiet
Standby Current
Measurement Condition
Timing Diagram
Example
Figure 2
CKE
HIGH
LOW
LOW
HIGH
External Clock
on
on
on
on
t_CK
t_CKmin(IDD)
t_CKmin(IDD)
t_CKmin(IDD)
t_CKmin(IDD)
t_RC
n.a.
n.a.
n.a.
n.a.
t_RAS
n.a.
n.a.
n.a.
n.a.
t_RCD
n.a.
n.a.
n.a.
n.a.
t_RRD
n.a.
n.a.
n.a.
n.a.
CL
n.a.
n.a.
n.a.
n.a.
AL
n.a.
n.a.
n.a.
n.a.
CS
HIGH
STABLE
STABLE
HIGH
Bank Address, Row SWITCHING as
Addr. and Command described in
Inputs
Table 2
STABLE
STABLE
STABLE
Data inputs
SWITCHING
FLOATING
FLOATING
FLOATING
Output Buffer
DQ,DQS
/ MR1 bit A12
off / 1
off / 1
off / 1
off / 1
ODT
disabled
/ MR1 bits [A6, A2] / [0,0]
disabled
/ [0,0]
disabled
/ [0,0]
disabled
/ [0,0]
Burst length
n.a.
n.a.
n.a.
n.a.
Active banks
none
none
none
none
Idle banks
all
all
all
all
Precharge Power
Down Mode /
n.a.
Mode Register Bit ^a
Fast Exit / 1
(any valid command
after tXP^b)
Slow Exit / 0
Slow exit (RD and n.a.
ODT commands must
satisfy tXPDLL-AL)
a.
b.
Rev. 0.1 / Dec 2008
39