MC9328MX21_06 Datasheet, PDF (93/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time
and setup time based on the following assumptions:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
≥ max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
≥ max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
3.22.2 Non-Gated Clock Mode
Figure 83 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 84 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 46. The formula for
calculating the pixel clock rise and fall time is located in Section 3.22.3, “Calculation of Pixel Clock Rise/
Fall Time.”
1
VSYNC
6
4
5
PIXCLK
DATA[7:0]
Valid Data
2
3
Valid Data
Valid Data
Figure 83. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
93