MC9328MX21_06 Datasheet, PDF (55/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
Table 36. SSI to SSI2 Ports Timing Parameters (Continued)
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
11a (Tx) CK high to STXD high
11b (Tx) CK high to STXD low
12 (Tx) CK high to STXD high impedance
13 SRXD setup time before (Rx) CK low
14 SRXD hold time after (Rx) CK low
0.34
0.72
0.34
0.72
ns
0.34
0.72
0.34
0.72
ns
0.34
0.48
0.34
0.48
ns
21.50
–
21.50
–
ns
0
–
0
–
ns
External Clock Operation (SSI2 Ports)
15 (Tx/Rx) CK clock period¹
90.91
–
16 (Tx/Rx) CK clock high period
36.36
–
17 (Tx/Rx) CK clock low period
36.36
–
18 (Tx) CK high to FS (bl) high
10.40
17.37
19 (Rx) CK high to FS (bl) high
11.00
19.70
20 (Tx) CK high to FS (bl) low
10.40
17.37
21 (Rx) CK high to FS (bl) low
11.00
19.70
22 (Tx) CK high to FS (wl) high
10.40
17.37
23 (Rx) CK high to FS (wl) high
11.00
19.70
24 (Tx) CK high to FS (wl) low
10.40
17.37
25 (Rx) CK high to FS (wl) low
11.00
19.70
26 (Tx) CK high to STXD valid from high impedance
9.59
17.08
27a (Tx) CK high to STXD high
9.59
17.08
27b (Tx) CK high to STXD low
9.59
17.08
28 (Tx) CK high to STXD high impedance
9.59
16.84
29 SRXD setup time before (Rx) CK low
2.52
–
30 SRXD hole time after (Rx) CK low
0
–
90.91
36.36
36.36
8.67
9.28
8.67
9.28
8.67
9.28
8.67
9.28
7.86
7.86
7.86
7.86
2.52
0
–
ns
–
ns
–
ns
15.88
ns
18.21
ns
15.88
ns
18.21
ns
15.88
ns
18.21
ns
15.88
ns
18.21
ns
15.59
ns
15.59
ns
15.59
ns
15.35
ns
–
ns
–
ns
Synchronous Internal Clock Operation (SSI2 Ports)
31 SRXD setup before (Tx) CK falling
32 SRXD hold after (Tx) CK falling
20.78
–
20.78
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (SSI2 Ports)
33 SRXD setup before (Tx) CK falling
34 SRXD hold after (Tx) CK falling
4.42
–
4.42
–
ns
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
55