MC9328MX21_06 Datasheet, PDF (25/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

BMI_CLK/CS
Specifications
BMI_READ_REQ
BMI_D[15:0]
Ttds
Ttdh
TxD
RxD
Ts
Ts
Trdh
Trh
Last TxD
BMI_WRITE
Read
BMI
Th
Write
BMI
Read
BMI
Figure 10. Memory Interface Slave Mode, External Bus Master Read/Write to BMI Timing
(MMD_MODE_SEL=0, MASTER_MODE_SEL=0)
Table 18. External Bus Master Read/Write to BMI Timing Table
Item
Write setup time
Write hold time
Receive data hold time
Transfer data setup time
Transfer data hold time
Read_req hold time
Symbol Minimum Typical Maximum
Unit
Ts
11
–
–
ns
Th
0
–
–
ns
Trdh
3
–
–
ns
Ttds
6
–
14
ns
Ttdh
6
–
14
ns
Trh
6
–
24
ns
Note: All the timings are assumed that the hclk is running at 133 MHz.
3.8.3 Connecting BMI to External Bus Slave Devices
In this mode the BMI_WRITE, BMI_READ and BMI_CLK/CS are output signals driving by the BMI
module. The output signal BMI_READ_REQ is still driving active-in on a write cycle, but it can be
ignored in this case. Instead, it is used to trigger internal logic to generate the read or write signals. Data
write cycles are continuously generated when TxFIFO is not emptied.
To issue a read cycle, the user can write a value of 1 to the READ bit of control register. This bit is cleared
automatically when the read operation is completed. A read cycle reads COUNT+1 data from the external
bus slave. The user can write a 1 to the READ bit while there is still data in the TxFIFO, but the read cycle
will not start until all data in the TxFIFO is emptied. If the read cycle begins, the write operation also
cannot begin until this read cycle complete.
In this master mode operation, Int_Clk is derived from HCLK through an integer divider DIV of BMI
control register and it is used to control the read/write cycle timing by generate WRITE and CLK/CS
signals.
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
25