MC9328MX21_06 Datasheet, PDF (48/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
Table 32. SDRAM Write Cycle Timing Parameter
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width
3.00
–
3
–
ns
2 SDRAM clock low-level width
3.00
–
3
–
ns
3 SDRAM clock cycle time
7.5
–
7.5
–
ns
4 Address setup time
3.67
–
2
–
ns
5 Address hold time
2.95
–
2
–
ns
6 Precharge cycle period¹
t_RP2
–
t_RP2
–
ns
7 Active to read/write command delay
t_RCD2
–
t_RCD2
–
ns
8 Data setup time
3.41
–
2
–
ns
9 Data hold time
2.45
–
2
–
ns
1. Precharge cycle timing is included in the write timing diagram.
2. t_RP and t_RCD = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
SDCLK
CS
13
2
RAS
6
CAS
WE
4
5
ADDR
BA
DQ
7
7
ROW/BA
DQM
48
Figure 40. SDRAM Refresh Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor