MC9328MX21_06 Datasheet, PDF (92/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
VSYNC
HSYNC
PIXCLK
1
2
7
5
6
DATA[7:0]
Valid Data
3
4
Valid Data
Valid Data
Figure 81. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
7
HSYNC
2
5
6
PIXCLK
DATA[7:0]
Valid Data
3
4
Valid Data
Valid Data
Figure 82. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 45. Gated Clock Mode Timing Parameters
Number
1
2
3
4
5
6
7
Parameter
csi_vsync to csi_hsync
csi_hsync to csi_pixclk
csi_d setup time
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
Minimum
9 * T_HCLK
3
1
1
T_HCLK
T_HCLK
0
Maximum
–
(T_P/2) - 3
–
–
–
–
HCLK / 2
Unit
ns
ns
ns
ns
ns
ns
MHz
HCLK = AHB System Clock, T_HCLK = Period for HCLK, T_P = Period of CSI_PIXCLK
MC9328MX21 Technical Data, Rev. 3.1
92
Freescale Semiconductor