MC9328MX21_06 Datasheet, PDF (16/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
Table 7 shows the power consumption for the device.
Table 7. Power Consumption
ID Parameter
Conditions
Symbol
Typ Max Units
1 Run Current QVDD = QVDDX = 1.65V, NVDD1 = 1.8V.
NVDD2 through NVDD6 = VDDA = 3.1V.
Core = 266 MHz, System = 133 MHz.
I_QVDD + I_QVDDX
I_NVDD1
120 – mA
8 – mA
MPEG4 Playback (QVGA) from MMC/SD card, 30fps, _{INVDD2 through INVDD6 + IVDDA 6.6 – mA}
44.1kHz audio.
2 Sleep Current Standby current with Well Biasing System enabled.
Well Bias Control Register (WBCR) must be set as
follows:
WBCR:
CRM_WBS bits = 01
CRM_WBFA bit = 1
CRM_WBM bits = 001
CRM_SPA_SEL bit = 1
FMCR bit = 1
I_STBY
QVDD = QVDDX = 1.65V, TA¹
– 1800 μA
QVDD = QVDDX = 1.65V, 25° – 700 μA
QVDD = QVDDX = 1.55V, 25° 320 – μA
For WBCR definition refer to System Control Chapter
in the reference manual.
1. TA = 70°C for suffixes VK, VM, DVK, DVM, and SVK. TA = 85°C for suffixes CVK, CVM, and SCVK.
3.4 AC Electrical Characteristics
The AC characteristics consist of output delays, input setup and hold times, and signal skew times. All
signals are specified relative to an appropriate edge of other signals. All timing specifications are specified
at a system operating frequency (HCLK) from 0 MHz to 133 MHz (core operating frequency 266 MHz)
with an operating supply voltage from V_{DD min} to V_{DD max} under an operating temperature from T_L to T_H.
All timing is measured at 30 pF loading with the exception of fast I/O signals as discussed below. Refer
to the reference manual’s System Control Chapter for details on drive strength settings.
Table 8 provides the maximum loading guidelines that can be tolerated on a memory I/O signal (also
known as Fast I/O) to achieve 133 MHz operation. These critical signals include the SDRAM Clock
(SDCLK), Data Bus signals (D[31:0]), lower order address signals such as A0-A10, MA10, MA11, and
other signals required to meet 133 MHz timing.
The values shown in Table 8 apply over the recommended operating temperature range. Care must be
taken to minimize parasitic capacitance of associated printed circuit board traces.
Table 8. Loading Guidelines for Fast IO Signals to Achieve 133MHz Operation
Drive Strength Setting (DSCR2–DSCR12)
Maximum I/O Loading at 1.8V Maximum I/O Loading at 3.0V
000: 3.5 mA
001: 4.5 mA
011: 5.5 mA
111: 6.5 mA
9 pF
12 pF
15 pF
19 pF
12 pF
16 pF
21 pF
26 pF
MC9328MX21 Technical Data, Rev. 3.1
16
Freescale Semiconductor