MC9328MX21_06 Datasheet, PDF (19/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
Table 12. Reset Module Timing Parameters
Ref
No.
Parameter
1 Width of input POWER_ON_RESET
2 Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
3 7k to 32k-cycle stretcher for SDRAM reset
4 14k to 32k-cycle stretcher for internal system reset HRESERT
and output reset at pin RESET_OUT
5 Width of external hard-reset RESET_IN
6 4k to 32k-cycle qualifier
1.8V ± 0.10V 3.0V ± 0.30V
Unit
Min Max Min Max
800 – 800 –
ms
300 300 300 300
ms
7
7
7
7 Cycles of CLK32
14 14 14 14 Cycles of CLK32
4
–
4
– Cycles of CLK32
4
4
4
4 Cycles of CLK32
3.7 External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to
request the DMAC for data transfer.
After assertion of External DMA request the DMA burst will start when the channel on which the External
request is the source (as per the RSSR settings) becomes the current highest priority channel. The external
device using the External DMA request should keep its request asserted until it is serviced by the DMAC.
One External DMA request will initiate one DMA burst.
The output External Grant signal from the DMAC is an active-low signal.When the following conditions
are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
• The DMA channel for which the DMA burst is ongoing has request source as external DMA Request
(as per source select register setting).
• REN and CEN bit of this channel are set.
• External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA
burst. As the external request is synchronized, the request synchronization will not be done during this
period. The priority of the external request becomes low for the next consecutive burst, if another DMA
request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and
Figure 5. Minimum and maximum timings for the External request and External grant signals are present
in Table 13.
Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External
DMA request is de-asserted immediately after sensing grant signal active.
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
19