MC9328MX21_06 Datasheet, PDF (49/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
Table 33. SDRAM Refresh Timing Parameters
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width
3.00
–
3
–
ns
2 SDRAM clock low-level width
3.00
–
3
–
ns
3 SDRAM clock cycle time
7.5
–
7.5
–
ns
4 Address setup time
3.67
–
2
–
ns
5 Address hold time
2.95
–
2
–
ns
6 Precharge cycle period
t_RP1
–
t_RP1
–
ns
7 Auto precharge command period
t_RC1
–
t_RC1
–
ns
1. t_RP and t_RC = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
DQM
CKE
BA
Figure 41. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
49