MC9328MX21_06 Datasheet, PDF (91/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
3.21 I²C Module
The I²C communication protocol consists of seven elements: START, Data Source/Recipient, Data
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP.
SDA
3
5
4
SCL
1
2
6
Figure 80. Definition of Bus Timing for I²C
Table 44. I²C Bus Timing Parameters
Ref
No.
Parameter
SCL Clock Frequency
1 Hold time (repeated) START condition
2 Data hold time
3 Data setup time
4 HIGH period of the SCL clock
5 LOW period of the SCL clock
6 Setup time for STOP condition
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
0
100
0
100
kHz
114.8
–
111.1
–
ns
0
69.7
0
72.3
ns
3.1
–
1.76
–
ns
69.7
–
68.3
–
ns
336.4
–
335.1
–
ns
110.5
–
111.1
–
ns
3.22 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for
statistic data generation, a status register, interface logic, a 32 × 32 image data receive FIFO, and a 16 × 32
statistic data FIFO.
3.22.1 Gated Clock Mode
Figure 81 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 82 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 45. The formula for
calculating the pixel clock rise and fall time is located in Section 3.22.3, “Calculation of Pixel Clock Rise/
Fall Time.”
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
91