MC9328MX21_06 Datasheet, PDF (5/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Signal Descriptions
2 Signal Descriptions
Table 2 identifies and describes the i.MX21 signals. Pin assignment is provided in Section 4, “Pin
Assignment and Package Information” and in the “Signal Multiplexing Scheme” table within the reference
manual.
The connections of the pins in Table 2 depends solely upon the user application, however there are a few
factory test signals that are not used in a normal application. Following is a list of these signals and how
they are to be terminated for proper operation of the i.MX21 processor:
• CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
• OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
• EXT_48M: To ensure proper operation, connect this signal to ground.
• EXT_266M: To ensure proper operation, connect this signal to ground.
• TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
• TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Signal Name
A [25:0]
D [31:0]
EB0
EB1
EB2
EB3
OE
CS [5:0]
ECB
LBA
BCLK
RW
DTACK
Table 2. i.MX21 Signal Descriptions
Function/Notes
External Bus/Chip Select (EIM)
Address bus signals
Data bus signals
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-
going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
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