MC9328MX21_06 Datasheet, PDF (26/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
3.8.3.1 Memory Interface Master Mode Without WAIT Signal
The WAIT control bit (BMICTLR1[29]) is used in this mode. When this bit is cleared (default), the
BMI_WAIT signal is ignored and the CS cycle is terminated by Wait State (WS) control bits. Figure 11
shows the BMI timing when the WAIT bit is cleared.
1+ws 1+ws
1+ws 1+ws
Int_Clk
(reference only)
Int_write
(reference only)
BMI_CLK/CS
BMI_READ_REQ
BMI_D[15:0]
BMI_WRITE
TxD1
TxD2
Last TxD
RxD1
Tdh
RxD2
BMI_READ
BMI write
BMI write
BMI write
DMA or CPU write data to TxFIFO
A 1 is written to READ bit of control reg1
On the next Int_Clk BMI issues a write cycle
BMI_READ_REQ is still logic high, BMI issues next write cycle
Figure 11. Memory Interface Master Mode, BMI Read/Write to External Slave Device Timing without Wait
Signal (MMD_MODE_SEL=0, MASTER_MODE_SEL=1)
3.8.3.2 Memory Interface Master Mode with WAIT Signal
When the WAIT control bit is set, the BMI_WAIT signal is used and the CS cycle is terminated upon
sampling a logic high BMI_WAIT signal. Figure 12 shows the BMI write timing when the WAIT bit is set.
When the BMI_WRITE is asserted, the BMI will detect the BMI_WAIT signal on every falling edge of
the Int_Clk. When it detected the high level of the BMI_WAIT, the BMI_WRITE will be negated after
1+WS Int_Clk period. If the BMI_WAIT is always high or already high before BMI_WRITE is asserted,
this timing will same as without WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS
Int_Clk period.
MC9328MX21 Technical Data, Rev. 3.1
26
Freescale Semiconductor