MC9328MX21_06 Datasheet, PDF (47/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
Table 31. SDRAM Read Cycle Timing Parameter (Continued)
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
4S Address setup time
3.67
–
2
–
ns
4H Address hold time
2.95
–
2
–
ns
5 SDRAM access time (CL = 3)
5 SDRAM access time (CL = 2)
5 SDRAM access time (CL = 1)
–
5.4
–
5.4
ns
–
6.0
–
6.0
ns
–
–
–
–
ns
6 Data out hold time
7 Data out high-impedance time (CL = 3)
7 Data out high-impedance time (CL = 2)
7 Data out high-impedance time (CL = 1)
8 Active to read/write command period (RC = 1)
2
–
–
–
t_RCD2
–
t_HZ1
t_HZ1
–
–
2
–
–
–
t_RCD2
–
ns
t_HZ1
ns
t_HZ1
ns
–
ns
–
ns
1. t_HZ = SDRAM data out high-impedance time, external SDRAM memory device dependent parameter.
2. t_RCD = SDRAM clock cycle time. The t_RCD setting can be found in the i.MX21 reference manual.
SDCLK
CS
13
2
RAS
6
CAS
WE
ADDR
DQ
4
5
/ BA
ROW/BA
7
COL/BA
8
9
DATA
DQM
Figure 39. SDRAM Write Cycle Timing Diagram
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
47