MC9328MX21_06 Datasheet, PDF (18/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
3.6 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 2 and
Figure 3. Be aware that NVDD must ramp up to at least 1.7V for NVDD1 and 2.7V for NVDD2-6 before
QVDD is powered up to prevent forward biasing.
POR
1
Can be adjusted depending on the crystal
start-up time 32kHz or 32.768kHz
RESET_POR
RESET_DRAM
2
Exact 300ms
HRESET
RESET_OUT
CLK32
3
7 cycles @ CLK32
4
14 cycles @ CLK32
HCLK
RESET_IN
HRESET
RESET_OUT
Figure 2. Timing Relationship with POR
5
14 cycles @ CLK32
4
6
CLK32
HCLK
18
Figure 3. Timing Relationship with RESET_IN
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor