MC9328MX21_06 Datasheet, PDF (6/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
BOOT [3:0]
SDBA [4:0]
SDIBA [3:0]
MA [11:0]
DQM [3:0]
CSD0
CSD1
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
EXTAL26M
XTAL26M
EXTAL32K
XTAL32K
CLKO
EXT_48M
EXT_266M
RESET_IN
RESET_OUT
POR
Function/Notes
Bootstrap
System Boot Mode Select—The operational system boot mode upon system reset is determined by the
settings of these pins. To hardwire these inputs low, terminate with a 1 KΩ resister to ground. For a logic
high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up.
Boot 3 should always be tied to logic low.
SDRAM Controller
SDRAM non-interleave mode bank address signals. These signals are multiplexed with address signals
A[20:16].
SDRAM interleave addressing mode bank address signals. These signals are multiplexed with address
signals A[24:21].
SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1].
SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2
corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0].
SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
SDRAM Row Address Select signal.
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
Clocks and Resets
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal
oscillator circuit is shut down. When using an external signal source, feed this input with a square wave
signal switching from GND to VDDA.
Oscillator output to external crystal. When using an external signal source, float this output.
32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square
wave signal switching from GND to QVDD5.
Oscillator output to external crystal. When using an external signal source, float this output.
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock
selection.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
MC9328MX21 Technical Data, Rev. 3.1
6
Freescale Semiconductor