MC9328MX21_06 Datasheet, PDF (58/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
control register PST. When the PST bit is set to a one, it means that a DS2502 is present; if the bit is set to
a zero, then no device was found.
3.17.2 Write 0
The Write 0 function simply writes a zero bit to the DS2502. The sequence takes 117 us. The one-wire bus
is held low for 100us.
Set WR0
AutoClear WR0
one-wire
BUS
Write 0 Slot 128us
100us
17us
Figure 47. Write 0 Timing
The Write 0 pulse sequence is initiated when the WR0 control bit register is set. When the write is
complete, the WR0 register will be auto cleared.
3.17.3 Write 1/Read Data
The Write 1 and Read timing is identical. The time slot is first driven low. According to the DS2502
documentation, the DS2502 has a delay circuit which is used to synchronize the DS2502 with the bus
master (one-wire). This delay circuit is triggered by the falling edge of the data line and is used to decide
when the DS2502 should sample the line. In the case of a write 1 or read 1, after a delay, a 1 will be
transmitted / received. When a read 0 slot is issued, the delay circuit will hold the data line low to override
the 1 generated by the bus master (one-wire).
For the Write 1 or Read, the control register WR1/RD is set and auto-cleared when the sequence has been
completed. After a Read, the control register RDST bit is set to the value of the read.
Set WR1/RD
Auto Clear WR1/R
Write “1” Slot 117us
5us
Figure 48. Write 1 Timing
MC9328MX21 Technical Data, Rev. 3.1
58
Freescale Semiconductor