MC9328MX21_06 Datasheet, PDF (32/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Specifications
T1
T1
VSYN
T2
HSYN
T3
XMAX
T4
T2
SCLK
Ts
LD[15:0]
Figure 22. Non-TFT Mode Panel Timing
Table 23. Non-TFT Mode Panel Timing
Symbol
Description
Minimum
Value
Unit
T1
HSYN to VSYN delay
2
HWAIT2+2
Tpix
T2
HSYN pulse width
1
T3
VSYN to SCLK
–
HWIDTH+1
Tpix
0 ≤ T3 ≤ Ts
–
T4
SCLK to HSYN
1
HWAIT1+1
Tpix
Note:
• Ts is the SCLK period while Tpix is the pixel clock period.
• VSYN, HSYN and SCLK can be programmed as active high or active low. In Figure 67, all these 3 signals are
active high.
• When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts.
• When it is in monochrome mode with bus width = 2, 4, and 8, T3 = 1, 2 and 4 Tpix respectively.
MC9328MX21 Technical Data, Rev. 3.1
32
Freescale Semiconductor