MC9328MX21_06 Datasheet, PDF (11/98 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
USBG_OE
USBG_ON
USBG_FS
USBH1_RXDP
USBH1_RXDM
USBH1_TXDP
USBH1_TXDM
USBH1_RXDAT
USBH1_OE
USBH1_FS
USBH_ON
USBH2_RXDP
USBH2_RXDM
USBH2_TXDP
USBH2_TXDM
USBH2_OE
USBH2_FS
USBG_SCL
USBG_SDA
USBG_TXR_INT
SD1_CMD
SD1_CLK
SD1_D[3:0]
SD2_CMD
SD2_CLK
SD2_D[3:0]
Function/Notes
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.
USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT
signal of USB OTG. This signal is muxed with SLCDC1_DAT10.
USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and
SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides
an alternative multiplex for UART4_CTS.
USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and
SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.
USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.
USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.
USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and
USBH1_RXDAT.
USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.
USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2.
USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2.
USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2.
USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2.
USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2.
USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2.
USB OTG I²C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8.
USB OTG I²C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7.
USB OTG transceiver interrupt input. Multiplexed with USBG_FS.
Secure Digital Interface
SD Command bidirectional signal—If the system designer does not want to make use of the internal pull-
up, via the Pull-up enable register, a 4.7k–69k external pull-up resistor must be added. This signal is
multiplexed with CSPI3_MOSI.
SD Output Clock. This signal is multiplexed with CSPI3_SCLK.
SD Data bidirectional signals—If the system designer does not want to make use of the internal pull-up,
via the Pull-up enable register, a 50k–69k external pull-up resistor must be added. SD1_D[3] is muxed
with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO.
SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1.
SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.
SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals
from SLCDC1.
MC9328MX21 Technical Data, Rev. 3.1
Freescale Semiconductor
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