MC912D60AVPVE8 Datasheet, PDF (92/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Bus Control and Input/Output
PIPOE — Pipe Status Signal Output Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime.
0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test
output signal from the CGM module).
1 = PE[6:5] are outputs and indicate the state of the instruction
queue (only effective in expanded modes).
NECLK — No External E Clock
Normal single chip: write once; special single chip: write anytime; all
other modes: write never. Read anytime. In peripheral mode, E is an
input and in all other modes, E is an output.
0 = PE4 is the external ECLK pin subject to the following limitation:
In single-chip modes, to get an ECLK output signal, it is
necessary to have ESTR = 0 in addition to NECLK = 0.
1 = PE4 is a general-purpose I/O pin.
LSTRE — Low Strobe (LSTRB) Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes or normal
expanded narrow mode.
0 = PE3 is a general-purpose I/O pin.
1 = PE3 is configured as the LSTRB bus-control output, provided
the MCU is not in single chip or normal expanded narrow
modes.
LSTRB is used during external writes. After reset in normal expanded
mode, LSTRB is disabled. If needed, it should be enabled before
external writes. External reads do not normally need LSTRB because
all 16 data bits can be driven even if the MCU only needs 8 bits of
data.
In normal expanded narrow mode this pin is reset to an output driving
high allowing the pin to be an output while in and immediately after
reset.
TAGLO is a shared function of the PE3/LSTRB pin. In special
expanded modes with LSTRE set and the BDM tagging on, a zero at
the falling edge of E tags the instruction word low byte being read into
the instruction queue.
Technical Data
92
Bus Control and Input/Output
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor