MC912D60AVPVE8 Datasheet, PDF (234/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Enhanced Capture Timer
Bit 7
6
5
FOC7
FOC6
FOC5
RESET:
0
0
0
CFORC — Timer Compare Force Register
4
FOC4
0
3
FOC3
0
2
FOC2
0
1
FOC1
0
Bit 0
FOC0
0
$0081
Read anytime but will always return $00 (1 state is transient). Write
anytime.
FOC[7:0] — Force Output Compare Action for Channel 7-0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
Bit 7
6
5
OC7M7 OC7M6 OC7M5
RESET:
0
0
0
OC7M — Output Compare 7 Mask Register
4
OC7M4
0
3
OC7M3
0
2
OC7M2
0
1
OC7M1
0
Bit 0
OC7M0
0
$0082
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding IOSn bit is set to be an output compare. This does not
change the state of the DDRT bits. At successful OC7, for each bit that
is set in OC7M, the corresponding data bit OC7D is stored to the
corresponding bit of the timer port.
NOTE:
OC7M has priority over output action on the timer port enabled by OMn
and OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the
action of corresponding OM and OL bits on the selected timer port.
Technical Data
234
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor