MC912D60AVPVE8 Datasheet, PDF (282/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Multiple Serial Interface
Normally data is transferred most significant bit first.This bit does not
affect the position of the MSB and LSB in the data register. Reads and
writes of the data register will always have MSB in bit 7.
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
SPSWAI SPC0
RESET:
0
0
0
0
0
0
0
0
SP0CR2 — SPI Control Register 2
$00D1
Read or write anytime.
SPSWAI — Serial Interface Stop in WAIT mode
0 = Serial interface clock operates normally
1 = Halt serial interface clock generation in WAIT mode
SPC0 — Serial Pin Control 0
This bit decides serial pin configurations with MSTR control bit.
Pin Mode
SPC0⁽¹⁾
MSTR
MISO⁽²⁾ MOSI⁽³⁾
SCK⁽⁴⁾
#1
Normal
0
#2
0
Slave Out Slave In SCK In
1
Master In Master Out SCK Out
#3
Bidirectional
1
#4
0
Slave I/O GPI/O
SCK In
1
GPI/O Master I/O SCK Out
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
SS⁽⁵⁾
SS In
SS I/O
SS In
SS I/O
Technical Data
282
Multiple Serial Interface
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor