MC912D60AVPVE8 Datasheet, PDF (162/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Clock Functions
11.7 System Clock Frequency formulas
See Figure 11-6:
SLWCLK = EXTALi / ( 2 x SLOW )
SLOW = 1,2,..63
SLWCLK = EXTALi
SLOW = 0
PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)
ECLK = SYSCLK / 2
XCLK = SLWCLK / 2
PCLK = SYSCLK / 2
BCLK⁽¹⁾ = EXTALi / 2
Boolean equations:
SYSCLK = (BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP &
BCSS & SLWCLK)
MCLK = (PCLK & MCS) | (XCLK & MCS)
MSCAN system = (EXTALi & CLKSRC) | (SYSCLK & CLKSRC)
BDM system = (BCLK & CLKSW) | (ECLK & CLKSW)
NOTE: During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are
supplied by VCO (PLLCLK).
11.8 Clock Divider Chains
Figure 11-6, Figure 11-7, Figure 11-8, and Figure 11-9 summarize the
clock divider chains for the various peripherals on the
MC68HC912D60A.
Technical Data
162
1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.
Clock Functions
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor