MC912D60AVPVE8 Datasheet, PDF (247/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Enhanced Capture Timer
Timer Registers
BIT 7
6
5
4
3
2
1
BIT 0
$00A4
BIt 7
6
5
4
3
2
1
Bit 0 PACN1 (hi)
$00A5
Bit 7
6
5
4
3
2
1
Bit 0 PACN0 (lo)
RESET:
0
0
0
0
0
0
0
0
PACN1, PACN0 — Pulse Accumulators Count Registers
$00A4, $00A5
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
in PBCTL, $B0) the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in
PBFLG ($B1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
BIT 7
6
5
4
3
MCZI MODMC RDMCL ICLAT
FLMC
RESET:
0
0
0
0
0
MCCTL — 16-Bit Modulus Down-Counter Control Register
2
MCEN
0
1
MCPR1
0
BIT 0
MCPR0
0
Read: any time
Write: any time
MCZI — Modulus Counter Underflow Interrupt Enable
0 = Modulus counter interrupt is disabled.
1 = Modulus counter interrupt is enabled.
$00A6
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Enhanced Capture Timer
Technical Data
247