MC912D60AVPVE8 Datasheet, PDF (87/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Bus Control and Input/Output
Registers
Bit 7
6
5
4
3
2
Single Chip PA7
PA6
PA5
PA4
PA3
PA2
RESET:
—
—
—
—
—
—
Expanded ADDR15/ ADDR14/ ADDR13/ ADDR12/ ADDR11/ ADDR10/
& Periph: DATA15 DATA14 DATA13 DATA12 DATA11 DATA10
Expanded
narrow
ADDR15/ ADDR14/ ADDR13/ ADDR12/ ADDR11/ ADDR10/
DATA15/ DATA14/ DATA13/ DATA12/ DATA11/ DATA10/
DATA7 DATA6 DATA5 DATA4 DATA3 DATA2
PORTA — Port A Register
1
PA1
—
ADDR9/
DATA9
ADDR9/
DATA9/
DATA1
Bit 0
PA0
—
ADDR8/
DATA8
ADDR8/
DATA8/
DATA0
$0000
Bits PA[7:0] are associated respectively with addresses ADDR[15:8],
DATA[15:8] and DATA[7:0], in narrow mode. When this port is not used
for external addresses such as in single-chip mode, these pins can be
used as general-purpose I/O. DDRA determines the primary direction of
each pin. This register is not in the on-chip map in expanded and
peripheral modes. Read and write anytime.
Bit 7
6
5
DDA7
DDA6
DDA5
RESET:
0
0
0
DDRA — Port A Data Direction Register
4
DDA4
0
3
DDA3
0
2
DDA2
0
1
DDA1
0
Bit 0
DDA0
0
$0002
This register determines the primary direction for each port A pin when
functioning as a general-purpose I/O port. DDRA is not in the on-chip
map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Bus Control and Input/Output
Technical Data
87