MC912D60AVPVE8 Datasheet, PDF (252/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Enhanced Capture Timer
An IC register is empty when it has been read or latched into the holding
register.
A holding register is empty when it has been read.
NOVWx — No Input Capture Overwrite
0 = The contents of the related capture register or holding register
can be overwritten when a new input capture or latch occurs.
1 = The related capture register or holding register cannot be
written by an event unless they are empty (see IC Channels).
This will prevent the captured value to be overwritten until it is
read or latched in the holding register.
BIT 7
6
5
4
SH37
SH26
SH15
SH04
RESET:
0
0
0
0
ICSYS — Input Control System Control Register
3
TFMOD
0
2
PACMX
0
1
BUFEN
0
BIT 0
LATQ
0
$00AB
Read: any time
Write: May be written once (SMODN=1). Writes are always permitted
when SMODN=0.
SHxy — Share Input action of Input Capture Channels x and y
0 = Normal operation
1 = The channel input ‘x’ causes the same action on the channel
‘y’. The port pin ‘x’ and the corresponding edge detector is
used to be active on the channel ‘y’.
TFMOD — Timer Flag-setting Mode
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with
the use of the ICOVW register ($AA) allows a timer interrupt to be
generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
Technical Data
252
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor