MC912D60AVPVE8 Datasheet, PDF (237/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Enhanced Capture Timer
Timer Registers
MCCNT register ($B6, $B7) clears the MCZF flag in the
MCFLG register ($A7). This has the advantage of eliminating
software overhead in a separate clear sequence. Extra care is
required to avoid accidental flag clearing due to unintended
accesses.
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
TQCR — Reserved
$0087
Bit 7
6
5
4
3
2
1
Bit 0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
RESET:
0
0
0
0
0
0
0
0
TCTL1 — Timer Control Register 1
$0088
Bit 7
6
5
4
3
2
1
Bit 0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
RESET:
0
0
0
0
0
0
0
0
TCTL2 — Timer Control Register 2
$0089
Read or write anytime.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output
action to be taken as a result of a successful OCn compare. When
either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
NOTE: To enable output action by OMn and OLn bits on the timer port, the
corresponding bit in OC7M should be cleared.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Enhanced Capture Timer
Technical Data
237