MC912D60AVPVE8 Datasheet, PDF (155/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Clock Functions
Limp-Home and Fast STOP Recovery modes
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Table 11-1. Summary of STOP Mode Exit Conditions
Mode
STOP exit without Limp Home
mode,
clock monitor disabled
Executing the STOP instruction
without Limp Home mode,
clock monitor enabled
STOP exit in Limp Home mode
with Delay
STOP exit in Limp Home mode
without Delay (Fast Stop
Recovery)
Conditions
Summary
NOLHM=1
CME=0
DLY=X
Oscillator must be stable within 4096 XCLK cycles. XCLK
can be modified by SLOW divider register.
Use of DLY=0 only recommended with external clock.
NOLHM=1
CME=1
DLY=X
When a STOP instruction is executed the MCU resets via
the clock monitor reset vector.
NOLHM=0
CME=X
DLY=1
Oscillator must be stable within 4096
f_VCOMIN cycles or there is a possibility of code runaway as
the clock monitor circuit can be misled by EXTALi clock
into reporting a good signal before it has fully stabilised
NOLHM=0
CME=X
DLY=0
This mode is only recommended for use with an external
clock source.
Table 11-2. Summary of Pseudo STOP Mode Exit Conditions
Mode
Pseudo-STOP exit in Limp Home
mode with Delay
Pseudo-STOP exit
in Limp Home mode without
Delay (Fast Stop Recovery)
Pseudo-STOP exit without Limp
Home mode, clock monitor
enabled
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, with Delay
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, without Delay
Conditions
NOLHM=0
CME=X
DLY=1
NOLHM=0
CME=X
DLY=0
NOLHM=1
CME=1
DLY=X
NOLHM=1
CME=0
DLY=1
NOLHM=1
CME=0
DLY=0
Summary
CPU exits stop in limp home mode and oscillator running. If
the oscillator fails during pseudo-STOP and then recovers
there is a possibility of code runaway as the clock monitor
circuit can be misled by EXTALi clock into reporting a
good signal before it has fully stabilised
This mode is not recommended as it is possible that the
initial VCO clock frequency may be high enough to cause
code runaway.
When a STOP instruction is executed the MCU resets via
the clock monitor reset vector.
Oscillator starts operation following 4096 XCLK cycles
(actual controlled by SLOW mode divider).
This mode is only recommended for use with an external
clock source.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Clock Functions
Technical Data
155