MC912D60AVPVE8 Datasheet, PDF (325/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

MSCAN Controller
Programmer’s Model of Message Storage
17.12 Programmer’s Model of Message Storage
The following section details the organisation of the receive and transmit
message buffers and the associated control registers. For reasons of
programmer interface simplification the receive and transmit message
buffers have the same outline. Each message buffer allocates 16 bytes
in the memory map containing a 13 byte data structure. An additional
transmit buffer priority register (TBPR) is defined for the transmit buffers.
Figure 17-10. Message Buffer Organization
Address⁽¹⁾
01x0
01x1
01x2
01x3
01x4
01x5
01x6
01x7
01x8
01x9
01xA
01xB
01xC
01xD
01xE
01xF
Register name
Identifier register 0
Identifier register 1
Identifier register 2
Identifier register 3
Data segment register 0
Data segment register 1
Data segment register 2
Data segment register 3
Data segment register 4
Data segment register 5
Data segment register 6
Data segment register 7
Data length register
Transmit buffer priority register⁽²⁾
Unused
Unused
1. x is 4, 5, 6, or 7 depending on which buffer RxFG,
Tx0, Tx1, or Tx2 respectively.
2. Not applicable for receive buffers
17.12.1 Message Buffer Outline
Figure 17-11 shows the common 13 byte data structure of receive and
transmit buffers for extended identifiers. The mapping of standard
identifiers into the IDR registers is shown in Figure 17-12. All bits of the
13 byte data structure are undefined out of reset.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
325