MC912D60AVPVE8 Datasheet, PDF (214/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

Pulse Width Modulator
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
PWEN3 PWEN2 PWEN1 PWEN0
RESET:
0
0
0
0
0
0
0
0
PWEN — PWM Enable
$0042
Setting any of the PWENx bits causes the associated port P line to
become an output regardless of the state of the associated data
direction register (DDRP) bit. This does not change the state of the data
direction bit. When PWENx returns to zero, the data direction bit controls
I/O direction. On the front end of the PWM channel, the scaler clock is
enabled to the PWM circuit by the PWENx enable bit being high. When
all four PWM channels are disabled, the prescaler counter shuts off to
save power. There is an edge-synchronizing gate circuit to guarantee
that the clock will only be enabled or disabled at an edge.
Read and write anytime.
PWEN3 — PWM Channel 3 Enable
The pulse modulated signal will be available at port P, bit 3 when its
clock source begins its next cycle.
0 = Channel 3 is disabled.
1 = Channel 3 is enabled.
PWEN2 — PWM Channel 2 Enable
The pulse modulated signal will be available at port P, bit 2 when its
clock source begins its next cycle.
0 = Channel 2 is disabled.
1 = Channel 2 is enabled.
PWEN1 — PWM Channel 1 Enable
The pulse modulated signal will be available at port P, bit 1 when its
clock source begins its next cycle.
0 = Channel 1 is disabled.
1 = Channel 1 is enabled.
Technical Data
214
Pulse Width Modulator
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor